When verifying a digital hardware design specified using an HDL, the verification engineer is often interested to know whether the design has passed through a certain configuration of internal component signals, known as a “state”.
Modern HDLs can be executed on simulation systems to produce traces of how the signals change over time. In the case of processor cores, for example, the simulation can effectively run the machine code accepted by the design. When verifying a module within the design, a test harness known as a testbench can be used to supply the correct stimuli to the design.
The signal traces can often be very long, and in a format that makes ascertaining what has actually happened relatively difficult for an engineer to ascertain, especially, where the state of interest constitutes the behaviour of multiple components over time.